You are on page 1of 29

Pertemuan 7 Organisasi Input / Output

Processor

Memory

Bus

I/O device 1

I/O de vice n

Figure 4.1. A single-bus structure.

Setiap perangkat I/O mempunyai alamat yg unik.

2 cara pengalamatan: Memory mapped I/O: Alamat I/O menempati sebagian dari alamat memory, pada Motorola. I/O mapped I/O atau Seperated I/O: Alamat memory dan I/O terpisah; dibedakan dgn IN dan READ , OUT dan WRITE, digunakan pada Intel.

Address lines Bus Data lines Control lines

Address decoder

Control circuits

Data and status registers

I/O interf ace

Input dev ice

Figure 4.2. I/O interface for an input device.

ST ATUS

DIRQ KIRQ SOUT

SIN

CONTR OL 7 6 5 4

DEN 3

KEN 2 1 0

Figure 4.3. Registers in kyboard and display interf e aces.

WAITK

WAITD

Move TestBit Branc h=0 Move TestBit Branch=0 Move Move Compare Branc 0 h Move Call

#LINE,R0 #0,ST TUS A WAITK DA TAIN,R1 #1,ST TUS A WAITD R1,DATA OUT R1,(R0)+ #$0D,R1 WAITK #$0A,DA TA OUT PROCESS

Initialize memory pointer. Test SIN. Wait for character to be entered. Read character. Test SOUT. Wait for displa to becomeready y . Send characterto display . Store characterand adv ance pointer. Chec if Carriage Return. k If not, get anothercharacter. Otherwise, send Line Feed. Call a subroutineto process the input line.

Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.

Teknik tranfer melalui I/O I/O terprogram(programmed I/O): I/O terjadi dibawah kontrol langsung prosesor melalui program. Prosesor menunggu sampai operasi selesai. Interrupt driven: program mengeluarkan perintah I/O, kemudian melanjutkan untuk mengeksekusi yg lain,kalau I/O siap akan menginterusi.Prosesor bertanggung jawab, tapi tidak terikat terus. DMA: Direct Memory Access, I/O dan memory saling bertukar data tanpa melibatkan prosesor.

Program 1 COMPUTE routine

Program 2 PRINT routine

1 2 Interrupt occurs here

i i +1

Figure 4.5. Transfer of control through the use of interrupts.

Vdd Processor R I NTR INTR INTR1 INTR2 INTR n

Figure 4.6.An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.

Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

I NTR1

Processor

INTA1 INTR p

Dev ice

Dev ice

INTA p Priority arbitration circuit

Dev ice

Dev ice

(b) Arrangement of priority groups

Fi gure 4.8. Interrupt pri ori ty schemes.

Main Program

Move Clear BitSet BitSet . . .


READ

#LINE,PNTR EOL #2,CONTR OL #9,PS

Initialize buffer pointer. Clear end-of-line indicator. Enable keyboard interrupts. Set in terrupt-enable in the PS. bit

In terrupt-serviceroutine MoveMultiple R0-R1, (SP) Move PNTR,R0 MoveByte DATAIN,R1 MoveByte R1,(R0)+ Move R0,PNTR CompareByte #$0D,R1 Branc 0 h RTRN Move #1,EOL BitClear #2,CONTR OL MoveMultiple (SP)+,R0-R1 Return-from-in terrupt Sa e registersR0 and R1 on stac v k. Load addresspointer. Get input characterand store it in memory . Updatepointer. Chec if CarriageReturn. k Indicate end of line. Disable keyb oard interrupts. Restoreregisters R0 and R1.

RTRN

Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.

OSINIT

OSSER VICES SCHEDULER

Set in terrupt v ectors: Time-slice clo c k SCHEDULER Soft w are in terrupt OSSER VICES Keyb oard in terrupts IOData . . . Examine stac k to determine requested op eration. Call appropriate routine. Sa v e program state. Select a runnable pro cess. Restore sa v ed con text of new pro cess. Push new v alues for PS and PC on stac k. Return from in terrupt.
(a) OS initialization, services, and scheduler

IOINIT

Set pro cess status to Blo c ked. Initialize memory buffer address p oin ter and coun ter. Call device driv er to initialize device and enable in terrupts in the device in terface. Return from subroutine. Poll devices to determine source of in terrupt. Call appropriate driv er. If END = 1, then set pro cess status to Runnable. Return from in terrupt.
(b) I/O routines

IOD A T A

KBDINIT KBDD A T A

Enable in terrupts. Return from subroutine. Chec k device status. If ready , then transfer c haracter. If c haracter = CR, then { set END else set END = 0. Return from subroutine.
(c) Keyboard driver

= 1; Disable

in terrupts }

Figure 4.10. A few operating system routines.

15 T

13 S

10

4 X

3 N

2 Z

1 V

0 C

Trace Superv isor Interrupt Priority

Condition Codes

Figure 4.14. Processor status gister in the 68000 processor re .

Main program MOVE.L CLR ORI.B MOVE . . . READ MOVEM.L MOVEA.L MOVE.B MOVE.B MOVE.L CMPI.B BNE MOVE ANDI.B MOVEM.L RTE #LINE,PNTR EOL #4,CONTR OL #$100,SR Initialize buffer pointer. Clear end-of-line indicator. Set bit KEN. Setprocessorpriority to 1.

In terrupt-serviceroutine A0/D0, (A7) PNTR,A0 DATAIN,D0 D0,(A0)+ A0,PNTR #$0D,D0 RTRN #1,EOL #$FB,CONTR OL (A7)+,A0/D0 Save registers D0 on stac A0, k. Load addresspointer. Get input character. Store it in memory buffer. Updatepointer. Chec if CarriageReturn. k Indicateend of line. Clear bit KEN. Restore registersD0, A0.

RTRN

Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

Figure 4.16. Part of the Pentium's processor status register.

Main program MOV MOV OR STI . . . READ PUSH PUSH MOV MOV MOV INC CMP JNE MOV X OR MOV POP POP IRET EOL,0 BL,4 CONTROL,BL

Set KEN to enable keyb oard in terrupts. Set in terruptflag in processor register.

In terrupt-serviceroutine EAX EBX EAX,PNTR BL,DATAIN [EAX],BL DWORDPTR[EAX] BL,0DH RTRN BL,4 CONTROL,BL EOL,1 EBX EAX Sa e registerEAX on stac v k. Sa e registerEBX on stac v k. Load addresspointer. Get input character. Storecharacter. Incremen PNTR. t Chec if characteris CR. k

RTRN

Clear bit KEN. Set EOL flag. Restore register EBX. Restore register EAX.

Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.

Disk

Disk

Netw ork Interf ce a

Figure 4.19. Use of DMA controllers in a computer system.

Figure 4.19. Use of DMA controllers in a computer system.

B BSY BR Processor DMA controller 1 DMA controller 2

BG1

BG2

Figure 4.20. A simple arrangement for b us arbitration using a daisy chain.

Antar muka (peripheral): rangkaian

penghubung antara perangkat I/O dgn bus komputer. Satu sisi memiliki jalur data ,alamat dan kontrol; sisi lain memiliki jalur data dan kontrol untuk mentransfer data ke perangkat I/O (port) Port paralel: mentransfer data dalam bentuk sejumlah bit 8 atau 16 secara simultan. Port serial: mengirim dan menerima data satu bit tiap satu waktu.

Parallel Transmission Example


Used for short distances (up to 6 meters) since bits sent in parallel mode tend to spread out over long distances

(8 separate copper wires)

Data Address R/W Master -ready Sla ve-ready Input interface DATAIN SIN Valid Data

Processor

Encoder and debouncing circuit

Key board switches

Figure 4.28. Keyboard to processor connection.

DATAOUT Processor CPU R/W Masteready Slave-ready Output interface Idle SOUT Valid Printer

Figure 4.31. Printer to processor connection.

Standar bus yang banyak digunakan. Bus Peripheral Component Interconnect (PCI).

Dikembangkan sebagai low cost, processor dependent,mengikuti perkembangan bandwidth bus untuk disk high speed, perangkat grafik, video dan sistem multiprosesor. high speed,untuk menghubungkan perangkat tambahan didalam atau diluar komputer seperti disk dan video display. serial ke peralatan seperti keyboard,kontrol game sampai internet.; kecepatan operasi: low speed(1.5Mbit/det), fullspeed(12Mbit/det), high speed (480Mbit/det)

SCSI (Small Computer System Interface); bus paralel

USB (Universal Serial Bus); menggunakan transmisi

Processor

Main memory

Processor b us Bridge PCI b us

Additional memory

SCSI controller SCSI b us

Ethernet interf ace

USB controller

ISA interf ace IDE disk

V ideo
Disk controller CD-R OM controller CDR OM

Disk 1

Disk 2

K eyboard

Game

Figure 4.38. An example of a computer system using different interface standards.

Fi gure 4.39. Use of a PCI bn a computer system. us i

Host computer Root hub

Hub

Hub

Hub

I/O de vice

I/O de vice

I/O de vice

I/O de vice

I/O de vice

I/O de vice

Figure 4.43. Universal Serial Bus tree structure.

Host computer Root Hub HS Hub A HS F/LS HS F/LS De vice C De vice D - High speed - Full/Lo w speed HS Hub B

Figure 4.44. Split bus operation