REPORT ON THE RESULTS OF INTERNSHIP

Name: Mileiko Serhii, 5th year master student, Drozd Myroslav, 1st year postgraduate student.
University: Odessa National Polytechnic University (ONPU). Place of internship: Newcastle University, Newcastle upon Tyne, United Kingdom Date of internship: 17.11.2011 17.12.2011 Supervisors: Prof. A. Yakovlev, Newcastle University Prof. A. Drozd, ONPU

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The task
1) To get acquainted with the research in the field EnergyModulated Computing and to connect it with subject of Diagnostics of Digital Components of Computer Systems. 2) To investigate the errors, which occur in digital components in case of using the energy-saving technologies

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Research of errors in digital circuits on condition of low Vdd Content

1. Introduction. Motivation, goal and structure

2. Restrictions and ways of experiment execution

3. Two types of errors

4. Estimation of a horizontal error

5. Conclusions

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Introduction
Motivation
1. Power-efficient modes can create conditions for occurrence of faults increasing amount of erroneous results.

2. This fact can reduce trustworthiness of results and can limit area application of energy-aware technologies.

3. The development of energy-aware technologies requires to research the nature of faults and errors arising from their use.
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Introduction
Goal and structure
The goal of research - to assess the nature of faults and errors arising from the use of energy-aware technologies

It is necessary to solve the following problems: To evaluate the possibilities of carrying out the experiments; To develop and improve tools for experiments to assess the faults and errors; Dynamically plan and carry out experiments, analyzing the results.
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Limitations and ways for carrying out the experiments

One source of failure in energy-saving technologies is reduction of power in digital circuits

Tool for experiments FPGA Altera design kit DE1

The main limitation for the experiments stand FPGA Altera design kit does not allow to lower the power of digital circuits

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Two types of errors

Assumption of two directions of result distortion caused by reduction of Vdd 1. Vertical errors caused by approximation of zero and unit levels. 2. Horizontal errors caused by deceleration of transient process in a digital circuit.

Vdd
T
7

Vdd

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Estimation of a horizontal error

Imitation of Vdd decrease by shortening a clock unit of calculation.
1. A circuit for learning a horizontal error
8 8 A MUL 16 2 D RG 16

B
0..65535 CLK 1 8 8 B A 16

4 D

RG 32

16

A
B

comp

RG

MUL 16 3

16

Calculation and output of error amount 8

Multiplier 2 is researched on a half of clock unit: CT 1 Check Multiplier 3 works during a clock unit: CT 1
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RG4 RG5

Comparison of errors obtained by two ways

Reducing a duration of impulse by decreasing of its duty cycle. Frequency F=50 MHz and clock duty cycle DC=10% or F=100 MHz and DC=20% define =2 nS. Table of Results
Project # T, nS 1, 7 2, 8 3, 9 4, 10 5, 11 6, 12 2,0 1,8 1,6 1,4 1,2 1,0 F=50MHz , DC=10% Error quantity Total 86 1726 12005 60116 65050 65282
Essential

F=100MHz , DC=20% Error quantity Total 114 2343 15127 61325 65176 65343
Essential

Error % Total 0,13 2,63 18,32 91,7 99,6 99,6

Essential

Error % Total 0,17 3,58 23,08 93,6 99,5 99,7

Essential

86 1726 10985 47495 51271 51020

100 100 91,50 79,0 78,8 78,2

114 2296 13938 46253 50631 50952

100 98,0 92,1 75,4 77,7 78,0

Conclusion: 1. Number of errors grows exponentially with reducing a duration of impulse; 2. Different results for T=2 nS in cases of F=50 MHz or F=100 MHz
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Reasons
2. Different results for T=2 nS in cases of F=50 MHz or F=100 MHz
Changing frequency needs to change the settings of phase locked loop (PLL) block and recompile the project Recompiled project programs FPGA in another way, and project with a small changes can have a big difference on FPGA and can have different signal ways length

Because of this, we have an inexact clock signal

In spite of this, we can consider the results relatively to the number of errors
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Values of errors
Factors are formed using counter (direct count). =2 nS.
# 1 Erroneous 1220 Correct 1420 Error -0200 # 11 Erroneous 0840 Correct 0A40 Error -0200 # 21 Erroneous 1C00 Correct 0000 Error 1C00

2
3 4 5 6 7 8 9 10

1000
D400 D000 4000 2E20 F000 1C00 FC00 1C60

0000
0000 0000 0000 3020 0000 0000 0000 1E60

1000
D400 D000 4000 -0200 F000 1C00 FC00 -0200

12
13 14 15 16 17 18 19 20

1C00
3500 2F80 21E0 4FC0 3580 35C0 3640 36C0

0000
1500 1F80 1FE0 3FC0 1580 15C0 1640 16C0

1C00
2000 1000 0200 1000 2000 2000 2000 2000

22
23 24 25 26 27 28 29 30

0DA0
E000 1C00 5200 1F20 5300 7FA0 5380 1C00

0BA0
0000 0000 3200 3F20 3300 5FA0 3380 0000

0200
E000 1C00 2000 -2000 2000 2000 2000 1C00

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Values of errors
Factors are formed using counter (direct count). =2 nS.
# 1 Erroneous 1220 Correct 1420 Error -0200 # 11 Erroneous 0840 Correct 0A40 Error -0200 # 21 Erroneous 1C00 Correct 0000 Error 1C00

2
3 4 5 6 7 8 9 10

1000
D400 D000 4000 2E20 F000 1C00 FC00 1C60

0000
0000 0000 0000 3020 0000 0000 0000 1E60

1000
D400 D000 4000 -0200 F000 1C00 FC00 -0200

12
13 14 15 16 17 18 19 20

1C00
3500 2F80 21E0 4FC0 3580 35C0 3640 36C0

0000
1500 1F80 1FE0 3FC0 1580 15C0 1640 16C0

1C00
2000 1000 0200 1000 2000 2000 2000 2000

22
23 24 25 26 27 28 29 30

0DA0
E000 1C00 5200 1F20 5300 7FA0 5380 1C00

0BA0
0000 0000 3200 3F20 3300 5FA0 3380 0000

0200
E000 1C00 2000 -2000 2000 2000 2000 1C00

Conclusions: Errors coloured red occur when one factor is equal to zero. Result also must be equal to zero, but isnt. The reasons of these errors are in transition from the previous result.
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Examination of typical error

Transition error XXFF (XX+1)00

This type of errors appears one of the first, and anxiously distorts the result. However, in actual computations such kind of transitions occurs very seldom Despite this, the study of such errors will not be superfluous

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Examination of typical error

This error occurs when second factor from the maximum turns into the minimum, whereas the first factor increases only by 1.

Assumption: Possibly, error appears due to the fact that some bits of the previous result, which contains many units do not have enough time to switch to zero?

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Examination of typical error

An experiment was conducted to validate this assumption.

The inputs of the multiplier were served alternately with two pairs of factors: 00FF and 0100. The result of the multiplication is always zero, thus there is no switching in the output of multiplier, and if the assumption is true, the errors should not occur.

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Examination of typical error

Results:
1. Errors in the transition from 0 to 0 appeared as often as other errors of this type. 2. Errors in the transition from 0100 to 00FF manifested earlier and occurred more often than in the transition from 00FF to 0100.
Conclusion: This type of error does not depend on the previous result, but depend on the previous input data. Perhaps this error is typical only for embedded dsp multiplier in Altera FPGA
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Values of errors
Factors are formed using counter (direct count). =2 nS.
# 1 Erroneous 1220 Correct 1420 Error -0200 # 11 Erroneous 0840 Correct 0A40 Error -0200 # 21 Erroneous 1C00 Correct 0000 Error 1C00

2
3 4 5 6 7 8 9 10

1000
D400 D000 4000 2E20 F000 1C00 FC00 1C60

0000
0000 0000 0000 3020 0000 0000 0000 1E60

1000
D400 D000 4000 -0200 F000 1C00 FC00 -0200

12
13 14 15 16 17 18 19 20

1C00
3500 2F80 21E0 4FC0 3580 35C0 3640 36C0

0000
1500 1F80 1FE0 3FC0 1580 15C0 1640 16C0

1C00
2000 1000 0200 1000 2000 2000 2000 2000

22
23 24 25 26 27 28 29 30

0DA0
E000 1C00 5200 1F20 5300 7FA0 5380 1C00

0BA0
0000 0000 3200 3F20 3300 5FA0 3380 0000

0200
E000 1C00 2000 -2000 2000 2000 2000 1C00

Conclusions: Difference between erroneous and correct result always has only one bit equal to 1 and other bits equal to 0. So we can see that these are single arithmetic errors. In most cases errors are positive, i. e. erroneous result is higher then correct
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Comparison of results at direct and reverse count

Direct count
# Factors Correct Erroneous 1 1460 0780 0380 Error -0400 Prev. Res. 076C 2 EB3F

Reverse count
# Factors Correct Erroneous Error 39D5 59D5 2000 Prev. Res. 3AC0

2
5 6

2180
4000 4800

1080
0000 0000 32A0 33E0 78A0

3080
C000 4000 72A0 53E0 98A0 3EE0 5680 4000

2000
C000 4000 4000 2000 2000

105F
3EC1 46B9 324F=519F

3
4 5

E93F
E73F E63F

3957
38D9 389A

5957
58D9 589A 55A6 3E15 37DF 538D 724F 1003

2000
2000 2000 2000

3A40
39C0 3980 3680=DA40

10 51A0 13 53A0 37 C1A0

8 DA3F 35A6 7E15 77DF 338D 324F 1203

338D=530F 11 CB9F 77DF=C19F 13 C19F

-4000 7EE0=CBA0 -4000 78A0=C1A0 2000 4000 -0200 33E0=53A0 32A0=51A0 1220

43 CBA0 7EE0 54 DA40 88 FE00 3680 0000

-4000 7E15=CB9F 54 539F 2000 4000 35A6=DA3F 56 519F FC03 66 1D9F

Conclusions: Previous and following results are replaced only for 5 errors (# 10-56 13-54 37-13 43-11 54-8 ). Direct count: Total amount of errors 88. Negative errors 10 (11,4%). Reverse count: Total amount of errors 66. Negative errors 14 (21,2%) .
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Comparison of essential and negative errors at direct and reverse count with step 1 and 3
Count # M Total U Amount L of errors % 1 Direct 2 3 4 1 Reverse 9953 47980 9979 24156 9937 15,2 73,2 15,2 36,9 15,2 Step 1 Essential Amount of errors 8906 33690 9102 20795 9349 % 89,5 70,2 91,2 86,1 94,1 Negative Amount of errors 2041 20081 3451 10572 2427 % 20,5 41,9 34,6 43,8 24,4 Total Amount of errors 5328 17278 8644 13316 3260 % 24,4 79,1 39,6 61,0 14,9 Step 3 Essential Amount of errors 4858 13821 7757 12047 3113 % 91,2 80,0 89,7 90,5 95,5 Negative Amount of errors 1428 7875 3189 4872 635 % 26,8 45,6 36,9 36,6 19,5

2
3 4

35899
13142 20567

54,8
20,1 31,4

28357
12218 18298

79,0
93,0 89,0

6486
2761 5939

18,1
21,0 28,9

18220
6398 16367

83,4
29,3 74,9

15757
5899 14555

86,5
92,2 88,9

2481
1299 5352

13,6
20,3 32,7

Conclusions: Table shows: high percent of essential errors in most significant bits (70,2%-95,5%), low percent of negative errors: 18%-46%, average 35%, 36% for direct count 21%, 23% for reverse count irrespectively of direction and step of count. big difference between results of multipliers
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Comparison of positive and negative errors in process of direct and reverse count
Total Count T, nS Amount of errors 2,292 Direct 1,875 1,458 2,292 Reverse 1,875 1,458 1006 5932 64254 1014 10962 64767 Positive Negative Average Average Average increment decrement increment of result by of result by of result positive negative by error error error 11369 7637 5405 9802 4455 135 3985 2344 130 3624 2582 16622 7777 4939 -7 6575 2932 5

%
1,54 9,01 98,4 1,55 16,8 99,2

Amount of errors 771 4328 1596 770 8589 64265

%
76,6 73,0 2,5 75,9 78,4 99,2

Amount of errors 235 1604 62658 244 2373 502

%
23,4 27,0 97,5 24,1 21,6 0,76

Conclusions: Reduction of T from 2,29 nS down to 1,46 nS decreases percent of positive errors from 76,6% down to 2,5% and increases percent of negative errors from 23,4% up to 97,5% reducing average increment of result from 7777 or 6575 down to -7 or 5.
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Comparison of positive and negative errors in case of random input words

Total (Tot) MUL T, nS Amount of errors 2,292 1 1,875 1,667 1,458 2,292 2 1,875 1,667 1,458 17934 61890 65228 65263 27586 62112 65263 65257 % 27,4 94,4 99,5 99,6 42,0 94,8 99,6 99,6 Amount of errors 13353 49442 41026 32622 18894 42707 32767 32616 % 74,5 79,9 62,9 50,0 68,5 68,8 50,2 50,0 Amount of errors 4582 12448 24202 32641 8691 19405 32496 32641 % 25,6 20,10 37,1 50,0 31,5 31,2 49,8 50,0 Positive (Pos) Negative (Neg) Average Average Average increment decrement increment of result of result by of result by positive negative by error error error 15908 20118 20617 15709 8716 13190 15980 15714 4407 9804 14320 15693 3180 7057 15673 15695 10718 14100 7654 3 4968 6864 219 3

Conclusions:

Examination of random input words case confirms decrease of average increment of result on condition of T reduction from 2,29 nS down to 1,46 nS.
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Comparison of positive and negative errors in case of random input words

100 90 80 70 60 50 40 30 20 10 0 2,3 1,9 1,7 1,5

MUL 1 Tot

Pos
Neg

T Examination of random input words case confirms decrease of average increment of result on condition of T reduction from 2,29 nS down to 1,46 nS.
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Conclusions:

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Conclusions
1. Reduction of Vdd can be imitated by cut of clock unit for examination of horizontal error 2. Small duration of clock unit defines high percent of essential errors (in most significant bits) and low percent of negative errors. 3. Reduction of clock unit duration decreases percent of positive errors and increases percent of negative errors reducing average increment of result. 4. The stable results of horizontal error research can be obtained only in framework of one ALTERA project.

5. It is necessary to continue the researches.

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The work done

1. 2. The subject of Energy-Modulated Computing developed in Newcastle University by prof. A. Yakovlev was studied. We studied the errors arising in the multiplier, which was built on the FPGA, used in low power modes. The investigations were performed on the Altera DE1 design kit. Because of the inability to lower the level of the energy consumption in DE1, the digital component was investigated in conditions of limited computation time. Reducing the computation time has influence similar to slowing down the calculations with decreasing power of digital components. We designed and investigated a scheme in which the results of multiplication with reduced computation time were compared with the correct results. The scheme allows to count the number of errors and to maintain the correct and erroneous results, when the errors occur, for their analysis. The experiments were performed with different input data flows: sequential, reverse sequential, sequential with different steps, random. We compared the errors at the outputs of several devices operating in parallel.
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The results of internship

Interests in the diagnosis of digital components of computer systems were expanded in the area of the Energy-Modulated Computing. We obtain experience in researching of digital components in the low power modes. Detected that errors, which occur in multiplier with limited computation time, are arithmetic, obtained depending of the number of positive and negative errors on the modes of computing time limits.

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Implementation/approbation of the results

The results of research were presented on the International Academic Conference of Young Scientists and students "Modern Information Technology 2012" and will be published in the scientific journal Electro-technical systems and components. Furthermore, the results of the researches will be presented in the Master student's qualifying work and PHD dissertation.

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